In electronics, a frequency synthesizer is a common component for generating signals having different frequencies e.g. in radio transmitters or receivers. A frequency synthesizer is usually implemented by a phase-locked loop. FIG. 1 shows a known implementation of a frequency synthesizer. A frequency synthesizer comprises a direct digital synthesizer 100 whose output 106 is coupled to the input of a phase-locked loop 102. A control signal 104 indicating the frequency the synthesizer shall generate is applied to the direct digital synthesizer.
A direct digital synthesizer is capable of very fast switching, or changing, of its output frequency. A typical switching value is below 1 .mu.s, but the signal generated thereby often contains too much noise and interference for telecommunication applications. Furthermore, only relatively low frequencies (about 100 MHz) can be achieved by digital synthesizers using present technology. This is why it is common to have a digital synthesizer followed by a phase-locked loop coupled in series. The phase-locked loop serves to purify the spectrum of the frequency synthesizer and transfer the frequency of the digital synthesizer to another, often higher, frequency. The phase-locked loop improves the spectrum of the frequency synthesizer by virtue of the loop filter, and with the help of the phase-locked loop the output signal of the frequency synthesizer to be shifted to the desired frequency range.
A problem in a phase-locked loop is that when the output frequency is changed, the loop is slow and it is often difficult to find the right compromise between the settling time of the phase-locked loop and suppression of noise and interference.
Some solutions are provided to solve the above problem. A known method increases the bandwidth of the phase-locked loop when the loop settles to a new frequency. The dual-speed loop filter required by such a solution is difficult to dimension, and the interference peaks from the required switches cause interference. At the moment of bandwidth change, the switches inject a charge into the loop filter capacitors. This results in a voltage step to the output of the voltage-controlled oscillator. With the phase-locked loop switched to slow operation mode, the voltage step will damp out only very slowly.
A known solution employs two phase detectors and two loop filters having different speeds and operated in parallel. The high-speed loop is used only when phase error is high, i.e. during the first part of synchronization. The low-speed loop is used when phase error is low, i.e. during the final part of synchronization and after synchronization. U.S. Pat. No. 5,142,246 discloses such a method. The large number of extra components required in this method is a drawback that makes the implementation expensive.
In another known solution, one or more division ratios in a phase-locked loop are adjusted during synchronization to compensate for one or more poles of the phase-locked loop transfer function, whereby the settling time shortens without increasing loop filter bandwidth. U.S. Pat. No. 5,371,480 teaches such a method. To simplify, the abrupt frequency step which appears at the input of the loop phase detector is predistorted to achieve an abrupt change in the output frequency of the loop. In order for this method to be effective, i.e. the predistorion to have sufficient resolution, the division factors of the phase-locked loop have to be relatively high. This is not a problem in conventional phase-locked loops, but when direct digital synthesizers are used with phase-locked loops, a high frequency resolution is obtained in the digital synthesizer, not in the phase-locked loop. In these cases the phase-locked loop is usually designed for high speed to keep the advantage of the fast switching of the digital synthesizer. In some cases a digital synthesizer is also used as a phase modulator. In this case, too, the phase-locked loop has to be fast for the phase modulation not to be distorted. To keep the phase noise of the phase-locked loop as low as possible, in spite of speed, small division factors must be chosen. This means that the frequency resolution of the phase-locked loop is not sufficiently high for pole compensation.